The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of providing a charge pump for generating high voltages and high currents for erasing and programming flash electrically-erasable programmable read only memory arrays (flash EEPROMs).
Flash EEPROMs play prominent and increasing roles in today""s computer systems. Flash EEPROMs must be able to operate in computer systems where a supply voltage (Vcc) of 5V, 3V, or even smaller voltage is available to the EEPROM devices. However, performing program and erase operations within an EEPROM device requires that greater voltages than that supplied to the EEPROM be applied to the memory cells within the EEPROM. For example, a program operation might require that approximately 10.5V be applied to a memory cell. A voltage of approximately xe2x88x9210.5V might be required to perform an erase operation. These voltages are achieved within the EEPROM device by charge pump circuits. A positive charge pump can take a supplied Vcc voltage and create a voltage sufficient for programing operations. A negative charge pump can take a supplied ground voltage and create a negative voltage sufficient for erase operations. The negative and positive charge pumps must also be able to deliver sufficient current at the required voltage levels.
FIG. 1 shows a typical prior art positive charge pump 130. The charge pump 130 includes a number of stages of N type field effect transistors 131, 132, 133, and 134 connected in series between a source voltage Vcc and an output terminal Vout. Clock signals 1 and 3 are supplied to the circuit 130 from sources 1 and 3, respectively, via capacitors 136, 137, and 138. Clock signals 2 and 4 are supplied to the circuit 130 from sources 2 and 4, respectively, via capacitors 140, 141, and 142. Each stage of the circuit 130 includes an N channel field effect transistor device 143, 144, or 145 used to control the voltage at the gate terminal of the device 131, 132, or 133 of that stage.
FIG. 2 shows the clock signals referred to as clock 1, clock 2, clock 3, and clock 4 associated with the circuit 130. In order to understand the operation of the circuit 130, the operation of a single stage including the switching transistor 132 will be discussed. Following the prior art timing diagram of FIG. 2, clocks 3 and 4 are initially high. Because clock 3 is high, the control device 144 is initially on. When the clock 1 signal goes high, the voltage pulse applied through the capacitor 136 charges the capacitor 141 at the gate terminal of the device 132 through the device 144 to the voltage level of the gate terminal of the device 144 minus a threshold voltage drop. When the clock 3 then goes low, the device 144 turns off, isolating the gate of the device 132 and leaving the capacitor 141 charged. This also lowers the voltage at the source of the device 132 so that the device 132 begins to conduct. When the clock 2 then goes high, the voltage at the gate is appreciably higher than at the drain because of the precharging of the capacitor 141. This turns the device 132 on in the region where it experiences no threshold voltage drop. The elimination of the threshold voltage drop means that the circuit can provide increased current from the capacitor 136 to the next stage. The high voltage at the capacitor 136 begins to charge the capacitor 137 and to discharge the capacitor 142 through the device 145.
When the clock 2 then goes low, the device 132 begins to turn off. When the clock 3 goes high, the device 144 turns on discharging the gate of the device 132 and bringing it toward the voltage of the drain so that the device 132 turns off. When the clock 1 then goes low, the device 132 stays off and the device 144 stays on so that the charge at the drain and gate are equalized.
Viewing the circuit as a whole, when the device 131 comes on in response to the high clock 4, its gate has been charged through the device 143 which has gone off. Thus, the device 131 turns on without a threshold voltage drop and charges the capacitor 136 rapidly. Then the device 131 begins to turn off as the clock 4 goes low. The rising clock 1 pulse completes the turnoff of the device 131 by discharging the capacitor 140 through the device 143. The high clock 1 continues the charging of the capacitor 141 until the drop of the clock 3 turns off the device 144 leaving the gate of the device 132 charged. The lowering of the clock 3 begins turning on the device 132 which comes on completely without a threshold voltage drop when the clock 2 goes high and the gate of the device 132 goes above the drain. This allows the charging of the capacitor 137. The same sequence continues through whatever number of stages are present until the charge on the capacitor 138 is sufficient to turn on the device 134 to provide a pumped voltage level at the output of the circuit 130. It should be noted that the last stage operates in a range in which it experiences a threshold voltage drop.
In addition to experiencing a threshold voltage drop in the last stage, prior pump circuits such as that discussed above have the disadvantage of being unable to provide adequate current when required to operate with supply voltages below approximately 3 V. For example, the pump circuit 130 discussed above would be unable to produce adequate current when supplied with 1.8 V and pumping up to a voltage of 10.5 V. An analogous situation exists with prior negative charge pumps, where a negative pump may need to pump to a voltage of approximately xe2x88x9212.5 V when a supply voltage of 1.8 V is supplied to a flash EEPROM.